Quantum computing with improved gate fidelity

Quantum computing has been around for several decades now, but still sounds a bit like a mysterious modern-day Holy Grail. In his Master thesis, Alexander Hungenberg (ETH Zurich) explains how a Red Pitaya STEMlab 125-14 helped increasing gate fidelity in an experimental setup.

Qubits are for quantum computing what bits are for classic computers: small units, carrying information using two-level quantum states. Input dependent operations on qubits are called gates, whose accuracy highly depends on gate fidelity, which needs to be >99.99% to implement error correction code at a reasonable level. The main technological challenge lies in creating physical systems with behaviors, close to this two-level description, with minimum quantum decoherence. The latter is the loss of quantum state, mainly due to interactions with the environment, resulting in less “pure” quantum state and in loss of the ability to exhibit quantum behavior. Trapping ions is one of the methods to create qubits, where entrapment is done using static DC and high-frequency RF electric fields.

The project, presented in the thesis, uses ⁴⁰Ca⁺ ions in a linear Paul-trap with four rod electrodes and two end-cap electrodes. It thereby focused on Rabi-flopping of a trapped calcium ion and on laser intensity noise as source of decoherence, as well as on data post-selection to increase gate fidelity. To do so, proper control of lasers and other devices was required for processes including readout, cooling, repumping, state preparation, gate operations or ionization, with wavelengths ranging between 375 and 866 nm and stable intensities and frequencies, as well as RF sources with proper timing control. The setup layout can be seen in Fig. 1, with the Red Pitaya unit clearly visible in the middle.

Figure 1: Experimental setup

In this setup, the STEMlab’s fast analog input channels captured laser intensity levels via photodiodes, placed in the beam after going through the trap. The resulting waveforms were then sent to a computer, running the ‘reptoar’ Python-based client software for further processing and storage. Both ADCs can produce big amounts of data, which were then pushed to the FPGA´s 16k sample ring buffer. In order to transfer this data efficiently, a direct-memory-access (DMA) solution was implemented, using a 64-bit AXI bus interface. This hardware configuration of the Red Pitaya unit can be seen in Fig. 2.

Figure 2: Connection diagram of the soft- and hard-core modules, involved in data acquisition on the Red Pitaya. Arrows point from master device to the connected slave. Red indicates the slow AXI-bus, while blue arrows are part of the DMA-based data path.

The postprocessing of the data was done on a workstation, running the ‘reptoar’-client Python program to keep track of the running experiment and using a configuration file to pass received waveforms to the indicated processing units. Besides high-speed DAQ, the STEMlab XADC module also allows long-term, slow-rate data logging, potentially useful for lab equipment monitoring over longer periods.

The document concludes with the successful outcome of the project, where post-selected data sets showed significant improvements with respect to longer coherence times. This post-selection not only improved gate fidelity, but also led to reduced sizes for data packages, obtained in an unstable lab environment. On the downside, there is still work to be done on individual shot reordering, based on measured pulse area.

The final statement, regarding future improvements on the ADC part of the setup, actually underlines Red Pitaya’s mission and motto: to be a “Swiss army knife for engineers” that provides a versatile, affordable tool for an infinite range of applications in their initial test phase, and which can later be substituted by higher-end, more specialized instruments.