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Easy FPGA project with Red Pitaya

Today with the advance of the technology we can implement the project with a FPGA (Field Programmable Gate Array). The FPGA is made with lots of logic blocks and each block contains logic gates, multiplexers, registers, etc. To implement the project the user of the FPGA has to make connections between these logic blocks and this is done with a HDL (Hardware Description Language). 


Red Pitaya uses Verilog and System Verilog as a HDL. Verilog is a HDL, it is very similar to the C programming language and it was developed in 1985. Verilog became popular because it is easy to learn if you have some programming experience with C. With Verilog you can describe the system in a sequential or in a combinational way and the most popular tools that are used to develop digital systems support Verilog.


The Red Pitaya board has a programmable logic made by Xilinx and to write it to describe your digital system you must use the software Vivado. Vivado is used to write your digital system with a HDL and to implement your system in the programmable logic. The result of the implementation of a Vivado project is a file called bitstream that has an extension .bit, that has the information about the connections of logic blocks that will be used and the connections between them. Click on the link for Vivado instalation tutorial.


After the installation of Vivado, we will have to clone the fpga repository and edit an existing project for our Hello World project. Go to the Red Pitaya GitHub site, and download the ZIP folder of this project. Go to the downloaded ZIP location and extract it. You will enter the fpga folder and make a Vivado project. Open a Terminal and input the following commands.


cd Downloads/

cd RedPitaya-master/

cd fpga/

. /opt/Xilinx/Vivado/2017.2/

make project PRJ=v0.94


For this project you will only have to edit the file. In the beggining of the file edit the port led_o assignment. Write the port as an output logic, as shown in the following image. You can navigate by the line number on the left side of the image.




Now edit this part of the file and comment the led_o port.




Finally insert this code at the end of the module that has a purpose of led blinking. Input that before endmodule: red_pitaya_top.


reg led = 1'b0;
reg [32-1 : 0] counter = 32'd0;
always @(posedge adc_clk) begin
if (counter < 32'd256000000) // 256e6 periods of clock of 128 MHz
counter <= counter +1;
else begin
led <= ~led ; // led will blink with a period of 4 sec
counter <= 32'd0; // start again
assign led_o[0] = led ; // assign the register to the led output


Now you have to start Synthesis, Implementation and Write bitstream. Press the green arrow button to start the synthesization. After finished synthesis continue with implementation and finish with write bitstream.




Now you have the bitstream file red_pitaya_top.bit located in …/fpga/prj/v0.94/project/repitaya.runs/impl_1. You have to send this file to your red pitaya board. Open a terminal and connect to red pitaya using ssh connection. In redpitaya enable read-write operation.


ssh root@your Red Pitaya IP

redpitaya> rw


Open another Terminal and go to the .bit file location.


cd Downloads/RedPitaya-master/fpga/prj/v0.94/project/repitaya.runs/impl_1


Send the file .bit to redpitaya with scp command.


scp red_pitaya_top.bit root@your Red Pitaya IP:/tmp


Go back to redpitaya Terminal, check if you have the copy red_pitaya_top.bit


redpitaya> cd /tmp


Load fpga.bin to xdevcfg with

redpitaya> cat /tmp/fpga.bin >/dev/xdevcfg


Congratulations the led should be blinking and you implemented the project in the FPGA.

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