FPGA-Based Dual-Channel Laser Servo: High-Bandwidth Deterministic Control on Red Pitaya

If you’ve spent weeks chasing a 1/f noise floor or fighting the phase-lag of a nested analog loop, you know the limitations of traditional PID boxes. While analog servos offer "infinite" resolution, they lack the agility for complex automated locks. Conversely, many digital solutions introduce OS-level jitter that kills the high-frequency performance required for narrow-linewidth lasers. 

This implementation moves the entire control logic into the FPGA fabric of a Red Pitaya STEMlab 125-14, providing a deterministic SIMO (Single Input, Multiple Output) architecture that rivals high-end commercial controllers. 

Technical Specifications at a Glance 

For the engineer comparing this to a Toptica FALC or a Vescent D2-125, here is the baseline performance of the Red Pitaya-based architecture: 

Beyond Simple PID: A SIMO Architecture for Laser Locking 

Most DIY digital locks fail because they treat the fast and slow actuators as separate problems. This architecture utilizes a Single Input, Multiple Output (SIMO) configuration. A single selectable error signal (from IN1 or IN2) feeds two parallel, independently configurable PID paths: 

1. Fast Path (Laser Current): Optimized for high-bandwidth feedback to suppress rapid frequency fluctuations and phase noise. 
2. Slow Path (Piezo/Thermal): Designed for high dynamic range to compensate for long-term drift without saturating the fast path. 

By integrating a symmetric triangular scan generator directly into the PID sum, the transition from "scanning" to "locked" is seamless. The system preserves the DC offset at the moment of lock-engagement, effectively eliminating the mode-hops that plague manual hand-offs. 

Integrated Lock-In: Eliminating the Rack of "Grey Boxes" 

In precision spectroscopy—specifically MTS (Modulation Transfer Spectroscopy) or FM spectroscopy—the signal-to-noise ratio is everything. Instead of an external lock-in amplifier, this design implements the following directly in the Verilog: 

• On-chip Modulation Generation: Synchronous with the demodulation clock for zero phase-drift. 
• Adjustable CIC (Cascaded Integrator-Comb) Filters: Allowing you to tune the trade-off between decimation rate and group delay. 
• Second-Harmonic Lock Detection: The FPGA monitors the $2f$ component to verify resonance. This enables "dark-start" capability—allowing your system to re-lock itself overnight without a human checking an oscilloscope. 
• Remote Gain Scheduling: Adjust P-I-D parameters over TCP/IP as environmental conditions change. 
• Automated Capture: Scripts that can "search and find" the resonance peak based on the $2f$ error signal. 
• Deterministic Timing: Moving all math to the FPGA means your loop bandwidth isn't at the mercy of a Linux kernel interrupt. 

Diagnostics without the Loading Effect 

One of the most valuable aspects for a photonics engineer is the diagnostic FIFO path. Because the data is tapped directly from the FPGA signal chain, you can stream raw ADC data or PID outputs for Power Spectral Density (PSD) analysis via MATLAB. This allows for real-time characterization of the closed-loop transfer function without the impedance loading or noise injection of external oscilloscope probes. 

The Shift to "Quantum-Ready" Infrastructure 

For those scaling from a single-table experiment to a multi-chamber trapped-ion or neutral atom array, the rack-space and cost of discrete PID controllers are prohibitive. 

This architecture matters because it treats the laser lock as a networked resource. By running a Python socket server on the Red Pitaya’s ARM processor to interface with the FPGA via the AXI bus, you gain: 

Technical Implementation & Repository 

The complete Bitstream, Verilog sources, and MATLAB/Python control classes are open-source and ready for deployment in your lab. 

Access the digital-laser-servo repository on GitHub.