In continuous-variable measurement-based quantum computing (CV-MBQC), the path to fault tolerance does not rely on scaling static physical qubits inside dilution refrigerators. Instead, it scales by entangling flying photons into high-dimensional spatiotemporal graph states. While this approach allows for room-temperature homodyne detection and leverages silicon photonics, it forces quantum hardware engineers to face a brutal classical control constraint: the propagation speed of the qubit.
Because computation in an MBQC framework progresses via sequential, destructive measurements, the selection of the measurement basis for any downstream mode is deterministically dictated by the outcomes of prior measurement events. Because photons travel at the speed of light (≈ 0.2 m/ns in silica fiber), the physical length of the optical buffer lines required to hold a photon while its companion is measured is defined entirely by the latency of the classical electronics loop.
If your data acquisition and processing stack introduces 1 microsecond of non-deterministic latency or software-induced operating system jitter, you must physically embed 200 meters of phase-stabilized fiber delay line into the machine for every single clock cycle buffer. For a multi-mode architecture, this requirement balloons into kilometers of fiber, introducing catastrophic optical attenuation, phase drift, and erasure errors that quickly breach fault-tolerant thresholds.
To minimize this physical buffer footprint, the classical control layer must execute homodyne quadrature extraction, feed-forward logic calculation, and optical switch modulation within a sub-microsecond window. In their Nature publication detailing Aurora—a modular photonic quantum architecture spanning 35 interconnected chips—Xanadu Quantum Technologies bypassed the latency penalties of standard computing platforms by deploying an array of Red Pitaya STEMlab 125-14 SoCs as the distributed, clock-synchronous hardware processing layer.
The modular architecture of Xanadu's Aurora system is split into three tightly timed physical stages, each requiring sub-nanosecond synchronization with the master clock:
1. Non-Gaussian State Generation & Pulsed Heralding
The system begins with 24 Gaussian Boson Sampling (GBS) source chips pumped by a customized pulsed laser system. These sources emit squeezed vacuum states and entangled two-mode Gaussian states. One mode is split off to Photon Number Resolving (PNR) detectors to herald the successful generation of non-Gaussian states. The companion mode is routed into a stabilized fiber delay line, which acts as the physical optical buffer while the classical electronics parse the heralding event.
2. Dynamic Multiplexing in Adaptive Refinery Trees
The heralded states feed six refinery chips engineered for state distillation and breeding. The refineries execute multiplexing via a binary tree of beam splitters and squeeze operators to synthesize entangled Gottesman-Kitaev-Preskill (GKP) Bell pairs. To maximize state-generation efficiency, the 4-to-1 binary tree multiplexers must actuate dynamically based on the real-time heralding decisions computed by the control layer during the previous clock cycle.
3. Spatiotemporal Lattices & Homodyne Measurement Gates
Five Quantum Processing Unit (QPU) chips accept the refined GKP Bell pairs. By using asymmetric fiber delay loops tuned precisely to the laser pulse repetition period, the QPUs interweave the traveling modes into a continuous spatiotemporal cluster-state lattice. Quantum operations are then executed on this resource state by performing balanced homodyne measurements on all 12 operating modes per clock cycle.
To compress the feed-forward loop tight enough to eliminate hundreds of meters of optical fiber routing, Xanadu eliminated the standard multi-board digitization loop (Standalone Digitizer --> PCIe Bus --> Host CPU --> DAC/Driver). This traditional loop introduces unpredictable latency variations due to OS thread scheduling and bus arbitration.
By placing Red Pitaya STEMlab boards directly at the intersection of the homodyne detectors and the optical switches, the system implements a completely flat, single-die processing topology.
14-Bit Synchronous Quadrature Extraction
The high-bandwidth analog transients emitted by the balanced homodyne detectors are routed to the Red Pitaya’s dual RF input channels, which sample at 125 MSps with a 14-bit resolution. The 14-bit ADC architecture yields 16,384 discrete vertical quantization steps. This provides the high dynamic range required to resolve fine-grained quadrature coordinates above the electronic noise floor, preventing quantization errors from skewing the threshold calculations.
Direct FPGA-to-I/O Feed-Forward Actuation
The raw digital samples flow straight from the ADC converters into the internal Xilinx FPGA fabric via parallel, on-die traces. Custom digital signal processing (DSP) blocks running within the FPGA handle filtering, baseline correction, and threshold discrimination within a handful of clock cycles.
Because the FPGA logic is hardwired directly to the board's high-speed digital I/O expansion pins, the calculated feed-forward decision is asserted instantly. These pins drive the modulation voltages for the refinery's binary switch trees, phase modulators, and squeezer pump-power modulators with nanosecond-level edge determinism—matching the speed of the traveling photons.
Multi-Node Clock Orchestration
To prevent timing drift from desynchronizing data across separate multi-rack assemblies, the distributed Red Pitaya boards operate under a shared hardware timeline. Utilizing their hardware expansion connectors, the units distribute a phase-locked master reference clock and synchronous global triggers. This ensures that every hardware node samples homodyne signals and actuates optical phase paths on the exact same nanosecond clock boundary.
The performance of the Xanadu Aurora machine confirms that distributed open-architecture SoC hardware can handle the deterministic speed requirements of CV-MBQC feed-forward loops. However, the data also highlights the massive scale of the control layer requirements for future architectures.
While the Aurora platform successfully verified the coexistence of all essential subsystems across 35 photonic chips, scaling to a production-grade fault-tolerant system deploying 100 logical qubits will require a massive expansion of the classical control infrastructure. As the spatiotemporal graph state scales, a commercial machine will require thousands of independent, highly parallelized FPGA processing nodes operating within a deeply hierarchical, ultra-low-latency cluster network to continuously decode error syndromes and execute real-time basis switching.
A standard high-speed PCIe digitizer relies on direct memory access (DMA) transfers to move data across the PCIe bus into host PC memory space, where an operating system thread must be awakened to process the signal and command a separate output card. Even with a real-time OS kernel, this path introduces several microseconds of non-deterministic latency and timing jitter. An integrated SoC like the STEMlab 125-14 routes the ADC outputs directly into the FPGA fabric on the same silicon die. The processing logic executes in hardware, and the control outputs are asserted via the digital I/O pins in nanoseconds, eliminating the host CPU bottleneck entirely.
The Red Pitaya open-source C API (rp.h) operates concurrently with the real-time FPGA fabric without interfering with its timing-critical loops. While the FPGA handles the sub-microsecond heralding and switch modulation loops in hardware, an application running on the embedded ARM Cortex-A9 processor can use the C API to read low-priority monitoring metrics from the DMA ring buffers, packaging and streaming them over standard UDP/IP links to a master laboratory dashboard (such as a LabVIEW control environment or Python based client) for diagnostic logging.
Yes. In addition to high-speed data acquisition, the STEMlab 125-14 features dual 14-bit RF digital-to-analog converter (DAC) channels operating up to 125 MSps. By compiling custom proportional-integral-derivative (PID) loop filters inside the FPGA fabric, engineers can configure the board to sample an optical cavity's interference fringes, compute real-time phase error corrections in hardware, and output high-speed analog correction voltages directly to an electro-optic modulator (EOM) or piezo actuator, acting as a standalone, high-bandwidth cavity locking system.