How ETH Zurich’s Trapped Ion Quantum Information Group integrated on-chip XADC sensing and dynamic FPGA sweep generators to achieve robust, hands-free Pound–Drever–Hall lock recovery.
In experimental quantum optics and trapped-ion quantum computing, laser frequency stability is non-negotiable. Quantum state manipulation, gate execution, and high-fidelity ion readout demand laser light locked tightly to optical reference cavities using techniques like Pound–Drever–Hall (PDH) frequency stabilization.
However, optical cavity stability faces a persistent physical vulnerability: acoustic noise, mechanical micro-vibrations, and thermal drifts. While Proportional-Integral (PI) feedback loops correct for continuous, small-scale frequency drifts, a strong shock can push the laser frequency outside the linear range of the PDH error signal. Historically, once a controller lost lock, operators were required to manually sweep the piezo actuator, locate resonance, and re-engage feedback loops—interruptions that degraded system uptime in complex quantum computing architectures.
To solve this automation bottleneck, the Trapped Ion Quantum Information (TIQI) Group at ETH Zürich developed an autonomous relocking mechanism built directly on the Red Pitaya STEMlab 125-14 platform.
Implemented on BLOOD (Bichannel Lockbox On One Device), this custom PI controller enables automatic lock recovery in under 100 ms after severe disturbances, eliminating the need for manual intervention. This enhancement was initially built as a software-driven feature by researcher Daria Panfilova and subsequently migrated into the hardware fabric by supervisor Bahadır Dönmez to achieve true deterministic performance. The project was overseen by Dr. Martin Stadler and Prof. Dr. Jonathan Home.
1. The Core Engineering Problem: The Narrow Linear Capture Window of PDH Locking
The Pound–Drever–Hall (PDH) technique generates an antisymmetric error signal by phase-modulating laser light prior to entering a Fabry–Pérot cavity. Near resonance, the PDH error signal acts as a steep derivative curve, providing a linear response that enables PI controllers to steer the laser frequency or piezo-driven cavity mirror back to nominal zero.
Figure 1: Timeline showing how the controller pauses the PI loop at lock loss (t0) and initiates triangular search sweeps with stepwise-increasing amplitudes until cavity resonance is rediscovered (t1). Image credit: Daria Panfilova, ETH Zürich
The fundamental limitation lies in the capture range. The linear region of a high-finesse optical cavity is narrow. When a sudden physical impact shifts the optical path length beyond this slope, the PDH error signal drops back to zero. To a standard PI controller, a zero-voltage error signal looks identical to perfect resonance. Consequently, the integral register accumulates error (windup), driving the piezo actuator to its voltage rails while the laser drifts out of lock.
2. System Architecture: Integrating Red Pitaya’s On-Chip XADC for Dual-Path Monitoring
Figure 2: The Red Pitaya STEMlab 125-14 board mounted directly onto the custom carrier PCB with analog interface electronics used in the TIQI laboratory. Image credit: Daria Panfilova, ETH Zürich
The BLOOD lockbox leverages the dual fast 14-bit ADC and DAC channels (125 MSps) of the Xilinx Zynq-7010 SoC on the Red Pitaya STEMlab 125-14 for its core PDH demodulation and PI feedback control loop.
To detect lock loss reliably without consuming one of the primary high-speed RF input channels, the ETH Zürich team modified the Linux device tree to access the Zynq processor's auxiliary analog-to-digital converter (XADC) via the Industrial I/O (IIO) subsystem.
Dual-Signal Sensing Strategy:
Figure 3: Block diagram illustrating the XADC trigger, the Zynq SoC converter, the Linux Industrial I/O (IIO) ring buffer, and the C++ server data streaming pipeline. Image credit: Daria Panfilova, ETH Zürich
By continuously sampling the transmission signal via the Zynq's auxiliary XADC, the embedded C++ server maintains a real-time monitor of optical coupling. If the transmission level drops below the user-defined software threshold, the server logic immediately classifies the system as 'unlocked,' freezes the PI loop integrator to prevent actuator windup, and initiates the relocking search sequence.
3. The Relocking Algorithm: Hardware-Driven Dynamic Amplitude Ramping
The core logic of the autonomous relocking system was initially developed and validated as a C++ software routine running on the Red Pitaya’s embedded Linux server. By combining software-driven control with the FPGA’s existing sweeper functionality, the system executes a structured, four-step recovery state machine:
4. Empirical Performance: Laboratory Validation on a Bow-Tie Optical Cavity
Figure 4: (a) Simplified optical schematic and (b) laboratory photograph of the frequency-doubling ultraviolet bow-tie cavity used to test the relocking algorithm. Image credit: Nicola Meggiato, ETH Zürich.
The automated relocking feature was subjected to benchtop verification using simulated signals and tested in an optics lab setup operating a frequency-doubling bow-tie cavity equipped with a piezo actuator.
Figure 5: Shows the full measurement sequence (the table knock, the unlock, the search, and the re-lock). Image credit: Daria Panfilova, ETH Zürich
Figure 6: A zoomed-in view of the relocking phase between t2 and t6. Image credit: Daria Panfilova, ETH Zürich
Key Performance Characteristics:
Figure 7: Relocking after temporarily blocking the beam. The system detects the loss of lockand automatically relocks once the beam is restored. Image credit: Daria Panfilova, ETH Zürich
If your optical bench requires both continuous cavity locking and nanosecond-precise pulse sequencing, check out our Comprehensive Red Pitaya Open-Source Selector Guide to see how BLOOD can be integrated into a synchronized dual-board Master/Slave architecture.
Initially, the team routed the XADC transmission levels into the C++ Linux server over the Industrial I/O (IIO) subsystem. However, relying on software drivers created complex synchronization lag between the XADC stream and the main oscilloscope channels. To solve this, the TIQI team migrated the relocking logic directly into the FPGA and upgraded the system to a native 3-channel hardware oscilloscope. This bypasses the OS software entirely, delivering perfect, deterministic phase-locking between the transmission monitor and the PDH error signals.
Using the primary fast ADCs (125 MSps, 14-bit) for low-frequency amplitude thresholding is an inefficient use of hardware resources. By routing the slow cavity transmission detector to the processor's internal XADC—operating at a fixed 31.25 kHz per channel (derived from a 125 kHz conversion trigger divided across four enabled analog inputs)—the STEMlab 125-14 preserves its second high-speed RF input for secondary fast channels, such as a second laser lock path or intensity stabilization loop (hence Bichannel Lockbox On One Device).
Lock-loss detection relies on strict user-defined upper and lower voltage limits applied to the cavity transmission signal. Through the custom graphical user interface (GUI), operators can visually monitor the real-time XADC transmission stream and fine-tune these thresholds to fit the specific noise floor of their bench, ensuring the sweep generator only triggers during a true lock-loss event.