Open-Source Experimental Control on Red Pitaya: A Comprehensive Review & Selector Guide

When setting up a laboratory, researchers face a choice: invest heavily in proprietary commercial instrumentation or spend months writing custom FPGA Hardware Description Language (HDL) code. Red Pitaya boards—combining ARM Cortex-A9 processors with programmable logic (PL)—bridge this gap. This review evaluates the primary open-source experimental control solutions available for Red Pitaya, detailing their architecture, specifications, ideal use cases, and limitations. 

1. The Master Framework Selector Matrix

The following comparison table synthesizes the primary execution models, timing specifications, and application targets across the Red Pitaya open-source control ecosystem:

⚠️ Critical Hardware Compatibility Warning: The specialized frameworks evaluated below (PyRPL, Linien, and OpenLabCtrl) are optimized for the converters and register layouts of the STEMlab 125-14 (or STEMlab 125-10) platforms. They are incompatible with the SIGNALlab 250-12, SDRlab 122-16, or STEMlab 125-14 4-Input models out of the box.

2. Architectural Selection Logic for Experimentalists

Run through the decision tree below to identify the optimal framework for your experimental bench:  

3. Architectural Selection Logic for Experimentalists

3.1. Software-Timed Control (SCPI & librp)

The host-PC SCPI server provides remote control of ADCs, DACs, and GPIOs for basic laboratory automation (e.g., sweeping DC bias levels). However, timing jitter is 1 ms – 10 ms due to TCP/IP stack overhead and host OS scheduling. Alternatively, the onboard C API (librp) allows standalone C programs to execute directly on the Zynq ARM CPU, bypassing the network stack to reduce loop latency to 10 µs – 100 µs, though it lacks nanosecond-scale FPGA determinism.

3.2. Continuous Analog Feedback & Laser Stabilization: PyRPL & Linien

When experiments require sub-microsecond analog feedback, software processing on the ARM CPU introduces unacceptable latency. Direct FPGA-based controllers execute high-speed DSP directly inside the logic to achieve 100 ns – 200 ns round-trip loop latencies at 125 MSa/s. 

PyRPL: Turns the Red Pitaya into a DSP lockbox achieving ~100 ns – 200 ns round-trip loop latencies at 125 MSa/s using memory-mapped register control. To actively compensate for physical equipment resonances (e.g., 25–90 kHz piezoelectric resonances), it includes an Infinite Impulse Response (IIR) module capable of implementing a 24-pole digital IIR filter as second-order biquad sections.

Linien: Purpose-built for Frequency Modulation Spectroscopy (FMS) and Modulation Transfer Spectroscopy (MTS). It features automated lock-point detection via a spectrum-to-instruction compiler, machine-learning-assisted parameter tuning (CMA-ES), and an "unlimited" second integrator for slow piezoelectric control in Extended Cavity Diode Lasers (ECDL) to prevent primary loop saturation.

3.3 High-Precision Deterministic Timing: OpenLabCtrl (RedPitaya-IO-Sync)

OpenLabCtrl is a deterministic sequencer designed as a lightweight alternative to ARTIQ. It provides strict 8 ns timing resolution across analog and digital IOs via hardware-gated DMA streaming, with sequences compiled in Python (IoSyncFrames library). While it operates strictly open-loop (lacking dynamic PID feedback), its fast sub-nanosecond digital outputs can externally gate GHz-frequency microwave sources or IQ mixers for pulsed quantum sensing (e.g., NV-centers).

3.4. Specialized Ecosystem & Community Projects

• Pavel Demin's Ecosystem
  • Offers open-source Vivado projects transforming the board into dedicated Vector Network Analyzers (VNA), multichannel analyzers (MCPHA), and Software Defined Radio (SDR) transceivers with native GNU Radio Companion integration.
• Koheron Control Stack
  • A C++/Python web development framework that uses fast C++ Linux drivers to map FPGA registers directly to Python. It automates the entire FPGA synthesis pipeline using Makefiles, bypassing the Vivado GUI for OEM product development.

3.5. Facility-Scale Middleware: EPICS & TANGO Integration

Exposes real-time hardware signals as network Process Variables (PVs) via an EPICS IOC or TANGO Device Servers for distributed diagnostics in large-scale physics facilities (e.g., CERN, DESY). 

4. The Hybrid Dual-Board Bench Architecture

Attempting to merge continuous PID feedback gateware and deterministic timing sequencer code onto a single Zynq-7010 SoC is highly resource-intensive due to FPGA logic cell constraints. Advanced laboratories resolve this by deploying a Master/Slave architecture: 

Master/Slave Synchronization Rules:

1.    Clock Synchronization (Phase Alignment): Both boards must phase-lock to a shared 10 MHz master reference clock fed into their dedicated external clock inputs to eliminate relative clock drift.  

2.    Trigger Synchronization (Timing Alignment): Board 2 (OpenLabCtrl) triggers Board 1 (PyRPL) via physical Digital IO (DIO) TTL lines or external SMA trigger connections to coordinate sequence starts.  

5. Next steps for your laboratory

Choosing the right open-source control framework ensures you achieve optimal timing precision and loop latency without spending valuable engineering hours on FPGA coding. Select the track below that matches your hardware setup:

🚀 Track 1: Download the OpenLabCtrl Repository and join the Early Access Program  

For Research groups that already own a STEMlab 125-14 and want to immediately deploy and test deterministic pulse sequencing.

• Action: Apply to join the OpenLabCtrl Early Access program using your existing hardware.
• Collaborate: Get direct access to the repository, test the framework in your live setup, report sequence timing bottlenecks, and submit feature requests directly to our core engineering team to help shape the roadmap.
• Link: Join Early Access with your hardware

📦 Track 2: Apply for an Evaluation Loaner Board and join the Early Access Program

For research groups building advanced time-domain protocols, coherent spin manipulation, or synchronized multi-sensor arrays who need evaluation hardware.

• Action: Apply to receive a complimentary 60-day physical evaluation loaner board.

• Collaborate: Test the framework in your live setup, share feedback on the Python API, report timing bottlenecks, and submit feature requests directly to our core engineering team. At the end of the trial, return the unit or purchase it with a 10% academic discount.

• Link: Apply for a Evaluation Loaner Board

Technical FAQ

Q: Can I run OpenLabCtrl, PyRPL, or Linien on Red Pitaya models other than the STEMlab 125-14 (e.g., SIGNALlab 250-12 or STEMlab 125-14 4-Input)?

A: Not natively. PyRPL, Linien, and OpenLabCtrl rely on specific memory-mapped FPGA register layouts, direct DMA memory allocations, and fixed ADC/DAC clocking pipelines designed explicitly for the dual-channel 14-bit converters of the STEMlab 125-14.

Q: Since the STEMlab 125-14 analog outputs are Nyquist-limited to 60 MHz, how can OpenLabCtrl be used for GHz-range quantum transitions (e.g., 2.87 GHz NV-center spin control)?

A: A: OpenLabCtrl operates as a high-speed timing orchestrator. Its sub-nanosecond digital outputs externally gate high-frequency microwave sources or IQ modulators, leveraging the 8 ns timing grid without being constrained by the board's analog DAC bandwidth.

Q: Can OpenLabCtrl perform dynamic conditional branching or closed-loop feedback based on live ADC input thresholding during a sequence?

A: A: No, it is strictly a deterministic open-loop sequencer streamed directly from host RAM. For sub-microsecond analog feedback, use PyRPL or Linien. For setups requiring both, deploy the dual-board architecture.